mmWD_UTCL1_STATUS_BASE_IDX 2309 drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_offset.h #define mmWD_UTCL1_STATUS_BASE_IDX                                                                     0
mmWD_UTCL1_STATUS_BASE_IDX  301 drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_0_offset.h #define mmWD_UTCL1_STATUS_BASE_IDX                                                                     0
mmWD_UTCL1_STATUS_BASE_IDX  297 drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_1_offset.h #define mmWD_UTCL1_STATUS_BASE_IDX                                                                     0
mmWD_UTCL1_STATUS_BASE_IDX  291 drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_2_1_offset.h #define mmWD_UTCL1_STATUS_BASE_IDX                                                                     0