mmWD_UTCL1_CNTL_BASE_IDX 2307 drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_offset.h #define mmWD_UTCL1_CNTL_BASE_IDX                                                                       0
mmWD_UTCL1_CNTL_BASE_IDX  299 drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_0_offset.h #define mmWD_UTCL1_CNTL_BASE_IDX                                                                       0
mmWD_UTCL1_CNTL_BASE_IDX  295 drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_1_offset.h #define mmWD_UTCL1_CNTL_BASE_IDX                                                                       0
mmWD_UTCL1_CNTL_BASE_IDX  289 drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_2_1_offset.h #define mmWD_UTCL1_CNTL_BASE_IDX                                                                       0