mmWD_UTCL1_CNTL  2306 drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_offset.h #define mmWD_UTCL1_CNTL                                                                                0x0fe3
mmWD_UTCL1_CNTL   298 drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_0_offset.h #define mmWD_UTCL1_CNTL                                                                                0x0243
mmWD_UTCL1_CNTL   294 drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_1_offset.h #define mmWD_UTCL1_CNTL                                                                                0x0243
mmWD_UTCL1_CNTL   288 drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_2_1_offset.h #define mmWD_UTCL1_CNTL                                                                                0x0243