mmWD_CNTL_SB_BUF_BASE 7450 drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_offset.h #define mmWD_CNTL_SB_BUF_BASE                                                                          0x2254
mmWD_CNTL_SB_BUF_BASE 4926 drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_0_offset.h #define mmWD_CNTL_SB_BUF_BASE                                                                          0x2254
mmWD_CNTL_SB_BUF_BASE 5178 drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_1_offset.h #define mmWD_CNTL_SB_BUF_BASE                                                                          0x2254
mmWD_CNTL_SB_BUF_BASE 5134 drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_2_1_offset.h #define mmWD_CNTL_SB_BUF_BASE                                                                          0x2254