mmWBIF0_SMU_WM_CONTROL_BASE_IDX 1571 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_1_0_offset.h #define mmWBIF0_SMU_WM_CONTROL_BASE_IDX                                                                2
mmWBIF0_SMU_WM_CONTROL_BASE_IDX 1219 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_0_0_offset.h #define mmWBIF0_SMU_WM_CONTROL_BASE_IDX                                                                2
mmWBIF0_SMU_WM_CONTROL_BASE_IDX 1181 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_1_0_offset.h #define mmWBIF0_SMU_WM_CONTROL_BASE_IDX                                                                2