mmVM_L2_CNTL4_BASE_IDX 1198 drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_0_offset.h #define mmVM_L2_CNTL4_BASE_IDX                                                                         0
mmVM_L2_CNTL4_BASE_IDX 1231 drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_1_offset.h #define mmVM_L2_CNTL4_BASE_IDX                                                                         0
mmVM_L2_CNTL4_BASE_IDX 1169 drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_2_1_offset.h #define mmVM_L2_CNTL4_BASE_IDX                                                                         0
mmVM_L2_CNTL4_BASE_IDX 1309 drivers/gpu/drm/amd/include/asic_reg/mmhub/mmhub_1_0_offset.h #define mmVM_L2_CNTL4_BASE_IDX                                                                         0
mmVM_L2_CNTL4_BASE_IDX 1341 drivers/gpu/drm/amd/include/asic_reg/mmhub/mmhub_9_1_offset.h #define mmVM_L2_CNTL4_BASE_IDX                                                                         0
mmVM_L2_CNTL4_BASE_IDX 1325 drivers/gpu/drm/amd/include/asic_reg/mmhub/mmhub_9_3_0_offset.h #define mmVM_L2_CNTL4_BASE_IDX                                                                         0