mmVGT_DMA_CONTROL_BASE_IDX 2345 drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_offset.h #define mmVGT_DMA_CONTROL_BASE_IDX                                                                     0
mmVGT_DMA_CONTROL_BASE_IDX  321 drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_0_offset.h #define mmVGT_DMA_CONTROL_BASE_IDX                                                                     0
mmVGT_DMA_CONTROL_BASE_IDX  317 drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_1_offset.h #define mmVGT_DMA_CONTROL_BASE_IDX                                                                     0
mmVGT_DMA_CONTROL_BASE_IDX  311 drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_2_1_offset.h #define mmVGT_DMA_CONTROL_BASE_IDX                                                                     0