mmVGT_CNTL_STATUS_BASE_IDX 2297 drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_offset.h #define mmVGT_CNTL_STATUS_BASE_IDX                                                                     0
mmVGT_CNTL_STATUS_BASE_IDX  289 drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_0_offset.h #define mmVGT_CNTL_STATUS_BASE_IDX                                                                     0
mmVGT_CNTL_STATUS_BASE_IDX  285 drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_1_offset.h #define mmVGT_CNTL_STATUS_BASE_IDX                                                                     0
mmVGT_CNTL_STATUS_BASE_IDX  279 drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_2_1_offset.h #define mmVGT_CNTL_STATUS_BASE_IDX                                                                     0