mmVGA_TEST_CONTROL_BASE_IDX  589 drivers/gpu/drm/amd/include/asic_reg/dce/dce_12_0_offset.h #define mmVGA_TEST_CONTROL_BASE_IDX                                                                    1
mmVGA_TEST_CONTROL_BASE_IDX  423 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_1_0_offset.h #define mmVGA_TEST_CONTROL_BASE_IDX                                                                    1
mmVGA_TEST_CONTROL_BASE_IDX   67 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_0_0_offset.h #define mmVGA_TEST_CONTROL_BASE_IDX                                                                    1
mmVGA_TEST_CONTROL_BASE_IDX  131 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_1_0_offset.h #define mmVGA_TEST_CONTROL_BASE_IDX                                                                    1