mmVGA_SEQUENCER_RESET_CONTROL_BASE_IDX  557 drivers/gpu/drm/amd/include/asic_reg/dce/dce_12_0_offset.h #define mmVGA_SEQUENCER_RESET_CONTROL_BASE_IDX                                                         1
mmVGA_SEQUENCER_RESET_CONTROL_BASE_IDX  391 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_1_0_offset.h #define mmVGA_SEQUENCER_RESET_CONTROL_BASE_IDX                                                         1
mmVGA_SEQUENCER_RESET_CONTROL_BASE_IDX   35 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_0_0_offset.h #define mmVGA_SEQUENCER_RESET_CONTROL_BASE_IDX                                                         1
mmVGA_SEQUENCER_RESET_CONTROL_BASE_IDX   91 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_1_0_offset.h #define mmVGA_SEQUENCER_RESET_CONTROL_BASE_IDX                                                         1