mmVGA_MAIN_CONTROL_BASE_IDX  587 drivers/gpu/drm/amd/include/asic_reg/dce/dce_12_0_offset.h #define mmVGA_MAIN_CONTROL_BASE_IDX                                                                    1
mmVGA_MAIN_CONTROL_BASE_IDX  421 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_1_0_offset.h #define mmVGA_MAIN_CONTROL_BASE_IDX                                                                    1
mmVGA_MAIN_CONTROL_BASE_IDX   65 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_0_0_offset.h #define mmVGA_MAIN_CONTROL_BASE_IDX                                                                    1
mmVGA_MAIN_CONTROL_BASE_IDX  129 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_1_0_offset.h #define mmVGA_MAIN_CONTROL_BASE_IDX                                                                    1