mmVGA_INTERRUPT_CONTROL_BASE_IDX  581 drivers/gpu/drm/amd/include/asic_reg/dce/dce_12_0_offset.h #define mmVGA_INTERRUPT_CONTROL_BASE_IDX                                                               1
mmVGA_INTERRUPT_CONTROL_BASE_IDX  415 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_1_0_offset.h #define mmVGA_INTERRUPT_CONTROL_BASE_IDX                                                               1
mmVGA_INTERRUPT_CONTROL_BASE_IDX   59 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_0_0_offset.h #define mmVGA_INTERRUPT_CONTROL_BASE_IDX                                                               1
mmVGA_INTERRUPT_CONTROL_BASE_IDX  123 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_1_0_offset.h #define mmVGA_INTERRUPT_CONTROL_BASE_IDX                                                               1