mmVGA_HDP_CONTROL_BASE_IDX  571 drivers/gpu/drm/amd/include/asic_reg/dce/dce_12_0_offset.h #define mmVGA_HDP_CONTROL_BASE_IDX                                                                     1
mmVGA_HDP_CONTROL_BASE_IDX  405 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_1_0_offset.h #define mmVGA_HDP_CONTROL_BASE_IDX                                                                     1
mmVGA_HDP_CONTROL_BASE_IDX   49 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_0_0_offset.h #define mmVGA_HDP_CONTROL_BASE_IDX                                                                     1
mmVGA_HDP_CONTROL_BASE_IDX  109 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_1_0_offset.h #define mmVGA_HDP_CONTROL_BASE_IDX                                                                     1