mmVGA_CACHE_CONTROL_BASE_IDX  573 drivers/gpu/drm/amd/include/asic_reg/dce/dce_12_0_offset.h #define mmVGA_CACHE_CONTROL_BASE_IDX                                                                   1
mmVGA_CACHE_CONTROL_BASE_IDX  407 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_1_0_offset.h #define mmVGA_CACHE_CONTROL_BASE_IDX                                                                   1
mmVGA_CACHE_CONTROL_BASE_IDX   51 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_0_0_offset.h #define mmVGA_CACHE_CONTROL_BASE_IDX                                                                   1
mmVGA_CACHE_CONTROL_BASE_IDX  111 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_1_0_offset.h #define mmVGA_CACHE_CONTROL_BASE_IDX                                                                   1