mmUVD_VCPU_CNTL_BASE_IDX  189 drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_7_0_offset.h #define mmUVD_VCPU_CNTL_BASE_IDX                                                                       1
mmUVD_VCPU_CNTL_BASE_IDX  377 drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_1_0_offset.h #define mmUVD_VCPU_CNTL_BASE_IDX                                                                       1
mmUVD_VCPU_CNTL_BASE_IDX  659 drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_0_0_offset.h #define mmUVD_VCPU_CNTL_BASE_IDX                                                                       1
mmUVD_VCPU_CNTL_BASE_IDX  718 drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_5_offset.h #define mmUVD_VCPU_CNTL_BASE_IDX                                                                       1