mmUVD_VCPU_CACHE_SIZE5_BASE_IDX  637 drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_0_0_offset.h #define mmUVD_VCPU_CACHE_SIZE5_BASE_IDX                                                                1
mmUVD_VCPU_CACHE_SIZE5_BASE_IDX  696 drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_5_offset.h #define mmUVD_VCPU_CACHE_SIZE5_BASE_IDX                                                                1