mmUVD_VCPU_CACHE_SIZE2_BASE_IDX  187 drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_7_0_offset.h #define mmUVD_VCPU_CACHE_SIZE2_BASE_IDX                                                                1
mmUVD_VCPU_CACHE_SIZE2_BASE_IDX  375 drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_1_0_offset.h #define mmUVD_VCPU_CACHE_SIZE2_BASE_IDX                                                                1
mmUVD_VCPU_CACHE_SIZE2_BASE_IDX  625 drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_0_0_offset.h #define mmUVD_VCPU_CACHE_SIZE2_BASE_IDX                                                                1
mmUVD_VCPU_CACHE_SIZE2_BASE_IDX  684 drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_5_offset.h #define mmUVD_VCPU_CACHE_SIZE2_BASE_IDX                                                                1