mmUVD_VCPU_CACHE_SIZE1_BASE_IDX  183 drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_7_0_offset.h #define mmUVD_VCPU_CACHE_SIZE1_BASE_IDX                                                                1
mmUVD_VCPU_CACHE_SIZE1_BASE_IDX  371 drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_1_0_offset.h #define mmUVD_VCPU_CACHE_SIZE1_BASE_IDX                                                                1
mmUVD_VCPU_CACHE_SIZE1_BASE_IDX  621 drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_0_0_offset.h #define mmUVD_VCPU_CACHE_SIZE1_BASE_IDX                                                                1
mmUVD_VCPU_CACHE_SIZE1_BASE_IDX  680 drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_5_offset.h #define mmUVD_VCPU_CACHE_SIZE1_BASE_IDX                                                                1