mmUVD_VCPU_CACHE_SIZE1 92 drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_4_0_d.h #define mmUVD_VCPU_CACHE_SIZE1 0x3D39 mmUVD_VCPU_CACHE_SIZE1 63 drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_4_2_d.h #define mmUVD_VCPU_CACHE_SIZE1 0x3d85 mmUVD_VCPU_CACHE_SIZE1 69 drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_5_0_d.h #define mmUVD_VCPU_CACHE_SIZE1 0x3d85 mmUVD_VCPU_CACHE_SIZE1 85 drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_6_0_d.h #define mmUVD_VCPU_CACHE_SIZE1 0x3d85 mmUVD_VCPU_CACHE_SIZE1 182 drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_7_0_offset.h #define mmUVD_VCPU_CACHE_SIZE1 0x0585 mmUVD_VCPU_CACHE_SIZE1 370 drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_1_0_offset.h #define mmUVD_VCPU_CACHE_SIZE1 0x0585 mmUVD_VCPU_CACHE_SIZE1 620 drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_0_0_offset.h #define mmUVD_VCPU_CACHE_SIZE1 0x0245 mmUVD_VCPU_CACHE_SIZE1 679 drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_5_offset.h #define mmUVD_VCPU_CACHE_SIZE1 0x0143