mmUVD_VCPU_CACHE_SIZE0_BASE_IDX  179 drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_7_0_offset.h #define mmUVD_VCPU_CACHE_SIZE0_BASE_IDX                                                                1
mmUVD_VCPU_CACHE_SIZE0_BASE_IDX  367 drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_1_0_offset.h #define mmUVD_VCPU_CACHE_SIZE0_BASE_IDX                                                                1
mmUVD_VCPU_CACHE_SIZE0_BASE_IDX  617 drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_0_0_offset.h #define mmUVD_VCPU_CACHE_SIZE0_BASE_IDX                                                                1
mmUVD_VCPU_CACHE_SIZE0_BASE_IDX  676 drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_5_offset.h #define mmUVD_VCPU_CACHE_SIZE0_BASE_IDX                                                                1