mmUVD_VCPU_CACHE_SIZE0 91 drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_4_0_d.h #define mmUVD_VCPU_CACHE_SIZE0 0x3D37 mmUVD_VCPU_CACHE_SIZE0 61 drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_4_2_d.h #define mmUVD_VCPU_CACHE_SIZE0 0x3d83 mmUVD_VCPU_CACHE_SIZE0 67 drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_5_0_d.h #define mmUVD_VCPU_CACHE_SIZE0 0x3d83 mmUVD_VCPU_CACHE_SIZE0 83 drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_6_0_d.h #define mmUVD_VCPU_CACHE_SIZE0 0x3d83 mmUVD_VCPU_CACHE_SIZE0 178 drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_7_0_offset.h #define mmUVD_VCPU_CACHE_SIZE0 0x0583 mmUVD_VCPU_CACHE_SIZE0 366 drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_1_0_offset.h #define mmUVD_VCPU_CACHE_SIZE0 0x0583 mmUVD_VCPU_CACHE_SIZE0 616 drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_0_0_offset.h #define mmUVD_VCPU_CACHE_SIZE0 0x0243 mmUVD_VCPU_CACHE_SIZE0 675 drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_5_offset.h #define mmUVD_VCPU_CACHE_SIZE0 0x0141