mmUVD_VCPU_CACHE_OFFSET1_BASE_IDX  181 drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_7_0_offset.h #define mmUVD_VCPU_CACHE_OFFSET1_BASE_IDX                                                              1
mmUVD_VCPU_CACHE_OFFSET1_BASE_IDX  369 drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_1_0_offset.h #define mmUVD_VCPU_CACHE_OFFSET1_BASE_IDX                                                              1
mmUVD_VCPU_CACHE_OFFSET1_BASE_IDX  619 drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_0_0_offset.h #define mmUVD_VCPU_CACHE_OFFSET1_BASE_IDX                                                              1
mmUVD_VCPU_CACHE_OFFSET1_BASE_IDX  678 drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_5_offset.h #define mmUVD_VCPU_CACHE_OFFSET1_BASE_IDX                                                              1