mmUVD_SUVD_CGC_STATUS_BASE_IDX  157 drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_1_0_offset.h #define mmUVD_SUVD_CGC_STATUS_BASE_IDX                                                                 1
mmUVD_SUVD_CGC_STATUS_BASE_IDX  821 drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_0_0_offset.h #define mmUVD_SUVD_CGC_STATUS_BASE_IDX                                                                 1
mmUVD_SUVD_CGC_STATUS_BASE_IDX  496 drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_5_offset.h #define mmUVD_SUVD_CGC_STATUS_BASE_IDX                                                                 1