mmUVD_SUVD_CGC_STATUS   90 drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_5_0_d.h #define mmUVD_SUVD_CGC_STATUS                                                   0x3be5
mmUVD_SUVD_CGC_STATUS  106 drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_6_0_d.h #define mmUVD_SUVD_CGC_STATUS                                                   0x3be5
mmUVD_SUVD_CGC_STATUS  156 drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_1_0_offset.h #define mmUVD_SUVD_CGC_STATUS                                                                          0x03e5
mmUVD_SUVD_CGC_STATUS  820 drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_0_0_offset.h #define mmUVD_SUVD_CGC_STATUS                                                                          0x05a5
mmUVD_SUVD_CGC_STATUS  495 drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_5_offset.h #define mmUVD_SUVD_CGC_STATUS                                                                          0x008d