mmUVD_SUVD_CGC_CTRL_BASE_IDX   69 drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_7_0_offset.h #define mmUVD_SUVD_CGC_CTRL_BASE_IDX                                                                   1
mmUVD_SUVD_CGC_CTRL_BASE_IDX  159 drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_1_0_offset.h #define mmUVD_SUVD_CGC_CTRL_BASE_IDX                                                                   1
mmUVD_SUVD_CGC_CTRL_BASE_IDX  823 drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_0_0_offset.h #define mmUVD_SUVD_CGC_CTRL_BASE_IDX                                                                   1
mmUVD_SUVD_CGC_CTRL_BASE_IDX  498 drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_5_offset.h #define mmUVD_SUVD_CGC_CTRL_BASE_IDX                                                                   1