mmUVD_SUVD_CGC_CTRL   91 drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_5_0_d.h #define mmUVD_SUVD_CGC_CTRL                                                     0x3be6
mmUVD_SUVD_CGC_CTRL  107 drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_6_0_d.h #define mmUVD_SUVD_CGC_CTRL                                                     0x3be6
mmUVD_SUVD_CGC_CTRL   68 drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_7_0_offset.h #define mmUVD_SUVD_CGC_CTRL                                                                            0x03e6
mmUVD_SUVD_CGC_CTRL  158 drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_1_0_offset.h #define mmUVD_SUVD_CGC_CTRL                                                                            0x03e6
mmUVD_SUVD_CGC_CTRL  822 drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_0_0_offset.h #define mmUVD_SUVD_CGC_CTRL                                                                            0x05a6
mmUVD_SUVD_CGC_CTRL  497 drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_5_offset.h #define mmUVD_SUVD_CGC_CTRL                                                                            0x008e