mmUVD_SEMA_CNTL_BASE_IDX  123 drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_7_0_offset.h #define mmUVD_SEMA_CNTL_BASE_IDX                                                                       1
mmUVD_SEMA_CNTL_BASE_IDX  249 drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_1_0_offset.h #define mmUVD_SEMA_CNTL_BASE_IDX                                                                       1
mmUVD_SEMA_CNTL_BASE_IDX  477 drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_0_0_offset.h #define mmUVD_SEMA_CNTL_BASE_IDX                                                                       1
mmUVD_SEMA_CNTL_BASE_IDX  804 drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_5_offset.h #define mmUVD_SEMA_CNTL_BASE_IDX                                                                       1