mmUVD_SEMA_CNTL    78 drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_4_0_d.h #define mmUVD_SEMA_CNTL 0x3D00
mmUVD_SEMA_CNTL    38 drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_4_2_d.h #define mmUVD_SEMA_CNTL                                                         0x3d00
mmUVD_SEMA_CNTL    44 drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_5_0_d.h #define mmUVD_SEMA_CNTL                                                         0x3d00
mmUVD_SEMA_CNTL    55 drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_6_0_d.h #define mmUVD_SEMA_CNTL                                                         0x3d00
mmUVD_SEMA_CNTL   122 drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_7_0_offset.h #define mmUVD_SEMA_CNTL                                                                                0x0500
mmUVD_SEMA_CNTL   248 drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_1_0_offset.h #define mmUVD_SEMA_CNTL                                                                                0x0500
mmUVD_SEMA_CNTL   476 drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_0_0_offset.h #define mmUVD_SEMA_CNTL                                                                                0x01c0
mmUVD_SEMA_CNTL   803 drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_5_offset.h #define mmUVD_SEMA_CNTL                                                                                0x02ef