mmUVD_SEMA_CMD_BASE_IDX  137 drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_1_0_offset.h #define mmUVD_SEMA_CMD_BASE_IDX                                                                        1
mmUVD_SEMA_CMD_BASE_IDX  809 drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_0_0_offset.h #define mmUVD_SEMA_CMD_BASE_IDX                                                                        1
mmUVD_SEMA_CMD_BASE_IDX  794 drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_5_offset.h #define mmUVD_SEMA_CMD_BASE_IDX                                                                        1