mmUVD_RB_WPTR3_BASE_IDX  131 drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_7_0_offset.h #define mmUVD_RB_WPTR3_BASE_IDX                                                                        1
mmUVD_RB_WPTR3_BASE_IDX  291 drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_1_0_offset.h #define mmUVD_RB_WPTR3_BASE_IDX                                                                        1
mmUVD_RB_WPTR3_BASE_IDX  481 drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_0_0_offset.h #define mmUVD_RB_WPTR3_BASE_IDX                                                                        1
mmUVD_RB_WPTR3_BASE_IDX  568 drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_5_offset.h #define mmUVD_RB_WPTR3_BASE_IDX                                                                        1