mmUVD_RB_WPTR2_BASE_IDX   93 drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_7_0_offset.h #define mmUVD_RB_WPTR2_BASE_IDX                                                                        1
mmUVD_RB_WPTR2_BASE_IDX  215 drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_1_0_offset.h #define mmUVD_RB_WPTR2_BASE_IDX                                                                        1
mmUVD_RB_WPTR2_BASE_IDX  927 drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_0_0_offset.h #define mmUVD_RB_WPTR2_BASE_IDX                                                                        1
mmUVD_RB_WPTR2_BASE_IDX  558 drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_5_offset.h #define mmUVD_RB_WPTR2_BASE_IDX                                                                        1