mmUVD_RB_WPTR      48 drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_6_0_d.h #define mmUVD_RB_WPTR                                                           0x3c2a
mmUVD_RB_WPTR     102 drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_7_0_offset.h #define mmUVD_RB_WPTR                                                                                  0x042a
mmUVD_RB_WPTR     224 drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_1_0_offset.h #define mmUVD_RB_WPTR                                                                                  0x042a
mmUVD_RB_WPTR     936 drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_0_0_offset.h #define mmUVD_RB_WPTR                                                                                  0x05ea
mmUVD_RB_WPTR     547 drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_5_offset.h #define mmUVD_RB_WPTR                                                                                  0x00ae