mmUVD_RB_RPTR_BASE_IDX  101 drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_7_0_offset.h #define mmUVD_RB_RPTR_BASE_IDX                                                                         1
mmUVD_RB_RPTR_BASE_IDX  223 drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_1_0_offset.h #define mmUVD_RB_RPTR_BASE_IDX                                                                         1
mmUVD_RB_RPTR_BASE_IDX  935 drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_0_0_offset.h #define mmUVD_RB_RPTR_BASE_IDX                                                                         1
mmUVD_RB_RPTR_BASE_IDX  546 drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_5_offset.h #define mmUVD_RB_RPTR_BASE_IDX                                                                         1