mmUVD_RB_BASE_HI3_BASE_IDX  135 drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_7_0_offset.h #define mmUVD_RB_BASE_HI3_BASE_IDX                                                                     1
mmUVD_RB_BASE_HI3_BASE_IDX  295 drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_1_0_offset.h #define mmUVD_RB_BASE_HI3_BASE_IDX                                                                     1
mmUVD_RB_BASE_HI3_BASE_IDX  485 drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_0_0_offset.h #define mmUVD_RB_BASE_HI3_BASE_IDX                                                                     1
mmUVD_RB_BASE_HI3_BASE_IDX  562 drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_5_offset.h #define mmUVD_RB_BASE_HI3_BASE_IDX                                                                     1