mmUVD_RB_BASE_HI   45 drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_6_0_d.h #define mmUVD_RB_BASE_HI                                                        0x3c27
mmUVD_RB_BASE_HI   96 drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_7_0_offset.h #define mmUVD_RB_BASE_HI                                                                               0x0427
mmUVD_RB_BASE_HI  218 drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_1_0_offset.h #define mmUVD_RB_BASE_HI                                                                               0x0427
mmUVD_RB_BASE_HI  930 drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_0_0_offset.h #define mmUVD_RB_BASE_HI                                                                               0x05e7
mmUVD_RB_BASE_HI  541 drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_5_offset.h #define mmUVD_RB_BASE_HI                                                                               0x00ab