mmUVD_RBC_WPTR_POLL_CNTL_BASE_IDX  409 drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_1_0_offset.h #define mmUVD_RBC_WPTR_POLL_CNTL_BASE_IDX                                                              1
mmUVD_RBC_WPTR_POLL_CNTL_BASE_IDX  759 drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_0_0_offset.h #define mmUVD_RBC_WPTR_POLL_CNTL_BASE_IDX                                                              1
mmUVD_RBC_WPTR_POLL_CNTL_BASE_IDX  790 drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_5_offset.h #define mmUVD_RBC_WPTR_POLL_CNTL_BASE_IDX                                                              1