mmUVD_RBC_RB_WPTR_CNTL   74 drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_4_0_d.h #define mmUVD_RBC_RB_WPTR_CNTL 0x3DA6
mmUVD_RBC_RB_WPTR_CNTL   73 drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_4_2_d.h #define mmUVD_RBC_RB_WPTR_CNTL                                                  0x3da6
mmUVD_RBC_RB_WPTR_CNTL   79 drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_5_0_d.h #define mmUVD_RBC_RB_WPTR_CNTL                                                  0x3da6
mmUVD_RBC_RB_WPTR_CNTL   95 drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_6_0_d.h #define mmUVD_RBC_RB_WPTR_CNTL                                                  0x3da6
mmUVD_RBC_RB_WPTR_CNTL  200 drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_7_0_offset.h #define mmUVD_RBC_RB_WPTR_CNTL                                                                         0x05a6
mmUVD_RBC_RB_WPTR_CNTL  388 drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_1_0_offset.h #define mmUVD_RBC_RB_WPTR_CNTL                                                                         0x05a6
mmUVD_RBC_RB_WPTR_CNTL  684 drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_0_0_offset.h #define mmUVD_RBC_RB_WPTR_CNTL                                                                         0x0266
mmUVD_RBC_RB_WPTR_CNTL  785 drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_5_offset.h #define mmUVD_RBC_RB_WPTR_CNTL                                                                         0x02e6