mmUVD_RBC_RB_RPTR_ADDR 72 drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_4_0_d.h #define mmUVD_RBC_RB_RPTR_ADDR 0x3DAA mmUVD_RBC_RB_RPTR_ADDR 75 drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_4_2_d.h #define mmUVD_RBC_RB_RPTR_ADDR 0x3daa mmUVD_RBC_RB_RPTR_ADDR 81 drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_5_0_d.h #define mmUVD_RBC_RB_RPTR_ADDR 0x3daa mmUVD_RBC_RB_RPTR_ADDR 97 drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_6_0_d.h #define mmUVD_RBC_RB_RPTR_ADDR 0x3daa mmUVD_RBC_RB_RPTR_ADDR 204 drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_7_0_offset.h #define mmUVD_RBC_RB_RPTR_ADDR 0x05aa mmUVD_RBC_RB_RPTR_ADDR 392 drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_1_0_offset.h #define mmUVD_RBC_RB_RPTR_ADDR 0x05aa mmUVD_RBC_RB_RPTR_ADDR 692 drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_0_0_offset.h #define mmUVD_RBC_RB_RPTR_ADDR 0x026a mmUVD_RBC_RB_RPTR_ADDR 775 drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_5_offset.h #define mmUVD_RBC_RB_RPTR_ADDR 0x02df