mmUVD_RBC_RB_CNTL 70 drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_4_0_d.h #define mmUVD_RBC_RB_CNTL 0x3DA9 mmUVD_RBC_RB_CNTL 74 drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_4_2_d.h #define mmUVD_RBC_RB_CNTL 0x3da9 mmUVD_RBC_RB_CNTL 80 drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_5_0_d.h #define mmUVD_RBC_RB_CNTL 0x3da9 mmUVD_RBC_RB_CNTL 96 drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_6_0_d.h #define mmUVD_RBC_RB_CNTL 0x3da9 mmUVD_RBC_RB_CNTL 202 drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_7_0_offset.h #define mmUVD_RBC_RB_CNTL 0x05a9 mmUVD_RBC_RB_CNTL 390 drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_1_0_offset.h #define mmUVD_RBC_RB_CNTL 0x05a9 mmUVD_RBC_RB_CNTL 690 drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_0_0_offset.h #define mmUVD_RBC_RB_CNTL 0x0269 mmUVD_RBC_RB_CNTL 773 drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_5_offset.h #define mmUVD_RBC_RB_CNTL 0x02de