mmUVD_MPC_SET_MUX_BASE_IDX  173 drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_7_0_offset.h #define mmUVD_MPC_SET_MUX_BASE_IDX                                                                     1
mmUVD_MPC_SET_MUX_BASE_IDX  355 drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_1_0_offset.h #define mmUVD_MPC_SET_MUX_BASE_IDX                                                                     1
mmUVD_MPC_SET_MUX_BASE_IDX  605 drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_0_0_offset.h #define mmUVD_MPC_SET_MUX_BASE_IDX                                                                     1
mmUVD_MPC_SET_MUX_BASE_IDX  758 drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_5_offset.h #define mmUVD_MPC_SET_MUX_BASE_IDX                                                                     1