mmUVD_MPC_SET_MUXB1_BASE_IDX  171 drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_7_0_offset.h #define mmUVD_MPC_SET_MUXB1_BASE_IDX                                                                   1
mmUVD_MPC_SET_MUXB1_BASE_IDX  353 drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_1_0_offset.h #define mmUVD_MPC_SET_MUXB1_BASE_IDX                                                                   1
mmUVD_MPC_SET_MUXB1_BASE_IDX  603 drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_0_0_offset.h #define mmUVD_MPC_SET_MUXB1_BASE_IDX                                                                   1
mmUVD_MPC_SET_MUXB1_BASE_IDX  756 drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_5_offset.h #define mmUVD_MPC_SET_MUXB1_BASE_IDX                                                                   1