mmUVD_MPC_SET_MUXB1   59 drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_4_0_d.h #define mmUVD_MPC_SET_MUXB1 0x3D7C
mmUVD_MPC_SET_MUXB1   57 drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_4_2_d.h #define mmUVD_MPC_SET_MUXB1                                                     0x3d7c
mmUVD_MPC_SET_MUXB1   63 drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_5_0_d.h #define mmUVD_MPC_SET_MUXB1                                                     0x3d7c
mmUVD_MPC_SET_MUXB1   79 drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_6_0_d.h #define mmUVD_MPC_SET_MUXB1                                                     0x3d7c
mmUVD_MPC_SET_MUXB1  170 drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_7_0_offset.h #define mmUVD_MPC_SET_MUXB1                                                                            0x057c
mmUVD_MPC_SET_MUXB1  352 drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_1_0_offset.h #define mmUVD_MPC_SET_MUXB1                                                                            0x057c
mmUVD_MPC_SET_MUXB1  602 drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_0_0_offset.h #define mmUVD_MPC_SET_MUXB1                                                                            0x023c
mmUVD_MPC_SET_MUXB1  755 drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_5_offset.h #define mmUVD_MPC_SET_MUXB1                                                                            0x02d1