mmUVD_MPC_SET_MUXB0   58 drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_4_0_d.h #define mmUVD_MPC_SET_MUXB0 0x3D7B
mmUVD_MPC_SET_MUXB0   56 drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_4_2_d.h #define mmUVD_MPC_SET_MUXB0                                                     0x3d7b
mmUVD_MPC_SET_MUXB0   62 drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_5_0_d.h #define mmUVD_MPC_SET_MUXB0                                                     0x3d7b
mmUVD_MPC_SET_MUXB0   78 drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_6_0_d.h #define mmUVD_MPC_SET_MUXB0                                                     0x3d7b
mmUVD_MPC_SET_MUXB0  168 drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_7_0_offset.h #define mmUVD_MPC_SET_MUXB0                                                                            0x057b
mmUVD_MPC_SET_MUXB0  350 drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_1_0_offset.h #define mmUVD_MPC_SET_MUXB0                                                                            0x057b
mmUVD_MPC_SET_MUXB0  600 drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_0_0_offset.h #define mmUVD_MPC_SET_MUXB0                                                                            0x023b
mmUVD_MPC_SET_MUXB0  753 drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_5_offset.h #define mmUVD_MPC_SET_MUXB0                                                                            0x02d0