mmUVD_MPC_SET_MUXA1   57 drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_4_0_d.h #define mmUVD_MPC_SET_MUXA1 0x3D7A
mmUVD_MPC_SET_MUXA1   55 drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_4_2_d.h #define mmUVD_MPC_SET_MUXA1                                                     0x3d7a
mmUVD_MPC_SET_MUXA1   61 drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_5_0_d.h #define mmUVD_MPC_SET_MUXA1                                                     0x3d7a
mmUVD_MPC_SET_MUXA1   77 drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_6_0_d.h #define mmUVD_MPC_SET_MUXA1                                                     0x3d7a
mmUVD_MPC_SET_MUXA1  166 drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_7_0_offset.h #define mmUVD_MPC_SET_MUXA1                                                                            0x057a
mmUVD_MPC_SET_MUXA1  348 drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_1_0_offset.h #define mmUVD_MPC_SET_MUXA1                                                                            0x057a
mmUVD_MPC_SET_MUXA1  598 drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_0_0_offset.h #define mmUVD_MPC_SET_MUXA1                                                                            0x023a
mmUVD_MPC_SET_MUXA1  751 drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_5_offset.h #define mmUVD_MPC_SET_MUXA1                                                                            0x02cf