mmUVD_MPC_SET_MUXA0_BASE_IDX  165 drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_7_0_offset.h #define mmUVD_MPC_SET_MUXA0_BASE_IDX                                                                   1
mmUVD_MPC_SET_MUXA0_BASE_IDX  347 drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_1_0_offset.h #define mmUVD_MPC_SET_MUXA0_BASE_IDX                                                                   1
mmUVD_MPC_SET_MUXA0_BASE_IDX  597 drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_0_0_offset.h #define mmUVD_MPC_SET_MUXA0_BASE_IDX                                                                   1
mmUVD_MPC_SET_MUXA0_BASE_IDX  750 drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_5_offset.h #define mmUVD_MPC_SET_MUXA0_BASE_IDX                                                                   1