mmUVD_MPC_SET_MUXA0 56 drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_4_0_d.h #define mmUVD_MPC_SET_MUXA0 0x3D79 mmUVD_MPC_SET_MUXA0 54 drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_4_2_d.h #define mmUVD_MPC_SET_MUXA0 0x3d79 mmUVD_MPC_SET_MUXA0 60 drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_5_0_d.h #define mmUVD_MPC_SET_MUXA0 0x3d79 mmUVD_MPC_SET_MUXA0 76 drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_6_0_d.h #define mmUVD_MPC_SET_MUXA0 0x3d79 mmUVD_MPC_SET_MUXA0 164 drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_7_0_offset.h #define mmUVD_MPC_SET_MUXA0 0x0579 mmUVD_MPC_SET_MUXA0 346 drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_1_0_offset.h #define mmUVD_MPC_SET_MUXA0 0x0579 mmUVD_MPC_SET_MUXA0 596 drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_0_0_offset.h #define mmUVD_MPC_SET_MUXA0 0x0239 mmUVD_MPC_SET_MUXA0 749 drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_5_offset.h #define mmUVD_MPC_SET_MUXA0 0x02ce