mmUVD_MPC_SET_MUX   55 drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_4_0_d.h #define mmUVD_MPC_SET_MUX 0x3D7D
mmUVD_MPC_SET_MUX   58 drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_4_2_d.h #define mmUVD_MPC_SET_MUX                                                       0x3d7d
mmUVD_MPC_SET_MUX   64 drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_5_0_d.h #define mmUVD_MPC_SET_MUX                                                       0x3d7d
mmUVD_MPC_SET_MUX   80 drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_6_0_d.h #define mmUVD_MPC_SET_MUX                                                       0x3d7d
mmUVD_MPC_SET_MUX  172 drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_7_0_offset.h #define mmUVD_MPC_SET_MUX                                                                              0x057d
mmUVD_MPC_SET_MUX  354 drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_1_0_offset.h #define mmUVD_MPC_SET_MUX                                                                              0x057d
mmUVD_MPC_SET_MUX  604 drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_0_0_offset.h #define mmUVD_MPC_SET_MUX                                                                              0x023d
mmUVD_MPC_SET_MUX  757 drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_5_offset.h #define mmUVD_MPC_SET_MUX                                                                              0x02d2