mmUVD_MPC_SET_ALU_BASE_IDX  175 drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_7_0_offset.h #define mmUVD_MPC_SET_ALU_BASE_IDX                                                                     1
mmUVD_MPC_SET_ALU_BASE_IDX  357 drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_1_0_offset.h #define mmUVD_MPC_SET_ALU_BASE_IDX                                                                     1
mmUVD_MPC_SET_ALU_BASE_IDX  607 drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_0_0_offset.h #define mmUVD_MPC_SET_ALU_BASE_IDX                                                                     1
mmUVD_MPC_SET_ALU_BASE_IDX  760 drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_5_offset.h #define mmUVD_MPC_SET_ALU_BASE_IDX                                                                     1