mmUVD_JRBC_RB_WPTR  126 drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_7_0_offset.h #define mmUVD_JRBC_RB_WPTR                                                                             0x0509
mmUVD_JRBC_RB_WPTR  262 drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_1_0_offset.h #define mmUVD_JRBC_RB_WPTR                                                                             0x0509
mmUVD_JRBC_RB_WPTR  122 drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_0_0_offset.h #define mmUVD_JRBC_RB_WPTR                                                                             0x0100
mmUVD_JRBC_RB_WPTR  125 drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_5_offset.h #define mmUVD_JRBC_RB_WPTR                                                                             0x0100