mmUVD_JRBC_RB_CNTL  264 drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_1_0_offset.h #define mmUVD_JRBC_RB_CNTL                                                                             0x050a
mmUVD_JRBC_RB_CNTL  124 drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_0_0_offset.h #define mmUVD_JRBC_RB_CNTL                                                                             0x0101
mmUVD_JRBC_RB_CNTL  127 drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_5_offset.h #define mmUVD_JRBC_RB_CNTL                                                                             0x0101